8051 IP Cores | Documentation

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# 8051 IP Cores

## Free 8051 IP Cores

## Oregano 8051 IP Core

The 8051 IP Core was developed in cooperation with the Arbeitsgruppe CAD / TU-Wien. This processor core is binary compatible to the well known 8051 processor from Intel. Our 8051 IP core is available as a synthetizeable circuit description (VHDL).

The Oregano 8051 IP core offers faster program execution compared to the original 8051 devices since we have optimized the processor's architecture. Additonally the 8051 IP core offers some sort of parametrizeability.

The 8051 IP Core source code is available for free under the LGPL (Lesser General Public License).

## Open Cores T51

8052 compatible microcontroller core. A utility to create VHDL ROMs is also included. Two different top levels:

- T8052: Single cycle synchronous RAM/ROM, Wishbone bus interface for memory mapped peripherals
- T8032: Wishbone bus interface

#### Features

- All peripherals/interrupts implemented
- Single cycle per byte fetch
- Supports synchronous RAM/ROM
- Single cycle MOVX (8052)
- Optional second DPTR
- Technology independent
- Three stage pipeline

## Open Cores 8051 core

The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory.

#### Features

- 8-bit CPU optimized for control applicati
  ons
- Exstensive Boolean processing (single-bit logic) capabilities
- 64K Program Memory address space
- 64K Data Memory address space
- up to 64K bytes of on-chip Program Memory (ROM)
- 128 bytes of on-chip Data RAM
- 4, 8 bit wide, ports outputs (byte or bit addressable)
- 4, 8 bit wide, ports inputs (byte or bit addressable)
- Two 16-bit timer/counters
- 6-source/5-vector interrupt structure with two priority levels priority levels

## Commercial 8051 IP Cores

## e8051

The e8051 is the fastest available 8051/8052 embedded microcontroller core for ASICs and FPGAs, achieving peak processing speeds of up to 300 Mips in ASICs and up to or above 130 Mips in FPGAs (equivalent to 3.6 GHz/1.5 GHz clock rates in a conventional 8051)

A free evaluation kit download is available for running small test programs at full speed in the user's own target hardware. Adding a high-performance 8051 microcontroller to a project has never been easier, the e8051 block is simply dropped into the design, and programs developed using standard software tools.

The 8051 is the world's most popular 8-bit controller, widely used in control, interface and communications. The e8051, first licensed in 1996, has one of the longest track records of any high-speed embedded 8051 IP. A version of the e8051 core is used in the highly regarded Dallas Semiconductor DS89C450 ultra fast stand-alone microcontrollers, and in other well known devices.

## Cast R8051XC

The R8051XC is a configurable, single-chip, 8-bit microcontroller core that can implement a variety of fast processor variations executing the MCS® 51 instruction set. The efficient core design runs an average of 8.1 times faster than the 80C51. A rich set of optional features and peripherals enable designers to closely match the core with their specific application and hardware requirements (FPGA, ASIC, or structured ASIC). These options include interrupts, interfaces for serial communication, I2C and SPI interfaces, a timer system, I/O ports, a power management unit, a multiplication-division unit, a watchdog timer, DMA controller and a real-time clock. Integrated on-chip debugging is also available.

The R8051XC is an extension of our proven 8051 family of processor cores, which have been successfully implemented in a hundred different customer products. Designers can purchase a custom configuration by selecting a set of options that best meets their needs, or choose from these three prepackaged versions of the core:

- R8051XC-F is the fully-configurable version of the core, with all options included. This is the only version that allows the user to configure the core with any of the available options.
- R8051XC-A matches our earlier R8051, with a set of peripherals making it compatible with the Intel 80C31 (see details in the Configurations section).
- R80515XC-B matches our earlier R80515 core, with a set of peripherals making it compatible with the Siemens 80C515 and 80C517.

Representative ASIC implementation results for the different configurations range from under 9,000 gates for the R8051XC-A to under 47,000 for all available options (except debug). Speed ranges from 250 to 350 MHz and above, depending on the technology. Developed for easy reuse in ASIC and FPGA implementations, the core is strictly synchronous, with positive-edge clocking, no internal tri-states and a synchronous reset. Reference designs have been evaluated in a variety of technologies.

## Digital Core Design DP8051CPU

The DP8051CPU is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.

The DP8051CPU soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051CPU: Harvard where internal data and program buses are separated, and von Neumann with common program and external data bus. The DP8051CPU has a Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slower than the original implementation, without performance depletion.The DP8051CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

## CorePool FHG8051

The FHG8051 is a high performance, opcode compatible core version of the industry standard 8051 microcontroller for ASIC and FPGA implementations. Its parameter set enables the designer to enhance the CPU performance and to tailor the architecture to the applications needs.

#### Features

- 8-Bit Synthesizable Microcontroller Core
- Opcode and Cycle Equivalent to Industry Standard 8051
- Fully Static, Microcode Free Design
- Up to 64K Bytes Program Memory Address Space
- Up to 64K Bytes Data Memory Address Space
- Up to 256 Bytes Internal Data Memory
- Up to 128 Special Function Registers (SFR)
- Idle, Power Down Mode
- Programmable Clock and Wait State Generator
- Technology independent (FPGA and ASIC)
- Silicon proven
- Optional 7 Interrupt Sources in 2 Priority Levels or no Interrupt Unit
- Optional True 8051 Cycle Operation or Reduced Cycle Mode for Enhanced Performance
- Optional PCON, P1, P3 or Second DTPR Register
- Optional Area Reducing NOP Behaviour for MUL, DIV or DA Opcodes
- Optional Program Memory Write Mode